Modern semiconductor device packages are formed from multiple stacked layers of materials that may include numerous electrically active components that are electrically coupled together by metal conductor interconnects. Although aluminum conductors with silicon dioxide disposed between such interconnects have been used in the past, current practices in fabricating high speed semiconductor devices and have moved toward using a combination of copper interconnects with suitable dielectric materials or films sash as low-k dielectrics to take advantage of the superior conductivity of copper compared to aluminum and reduced parasitic capacitance between the conductors. This has reduced resistive capacitance delay (“RC delay”) which limits increases in clock speed in integrated circuits and semiconductor devices.
Back end-of-line (“BEOL”) processes are used to create the intricate network of conductor interconnects in each layer and between the multiple layers wherein copper is laid into the dielectric material. An additive patterning processes, referred to as damascene and dual damascene, are some BEOL process used to form the patterned copper conductor interconnect circuit(s) which interconnect various active components (e.g., resistors, transistors, etc.) disposed in the single and multiple layers throughout the microchip. Some of these interconnect circuit structures include trenches which are filled with the copper conductor and vias which are essentially metal-plated or filled holes that electrically connect the conductors between the layers in the semiconductor packages.
These open trench and via structures are formed in dielectric material using various photolithography and material removal processes such as anisotropic dry gas plasma etching. Dry etching is performed in an etcher machine by applying an electromagnetic energy source (such as RF) to a gas containing a suitable chemically reactive element that reacts with the material to be etched or removed. The gas plasma emits positively charged ions that strike and dissolve the dielectric material. By using a combination of hard masks and/or patterned photoresist layers above the dielectric material layer having openings configured in the shape of the circuit desired to be formed, various patterns of recessed trench and via openings can be made in the dielectric material since dielectric material beneath the hard mask and photoresist will not dissolve. Became the ions strike the dielectric material essentially perpendicular to its surface in anisotropic dry plasma etching, vertical trench and via profiles can be created with virtually no undercutting beneath the hard mask and photoresist.
After the trenches and vias are formed by dry etching, copper may be deposited in these open structures in the dielectric by any suitable known technique such as chemical vapor deposition (CVD), physical vapor deposition (PVD), Plasma-Enhanced Chemical Vapor Deposition (PECVD), electro-chemical plating (ECP), electroless-plating, etc. Subsequent processes such as chemical mechanical planarization (CMP) or etching may be used in some instances as needed to polish and plane the top surface of the dielectric material layer, thereby leaving an essentially flat surface on which subsequent layers of dielectric with interconnects can be built.
Line-to-line capacitance (between interconnect lines) has become an increasingly limiting factor on microprocessor clock speeds as processes have been scaled down, for example to current 90 nm (nanometer) and 65 nm processes, and newest 45 nm process. Low-k dielectric materials, such as Black Diamond® available from Applied Materials, Incorporated® which has a dielectric constant (k) lower than 3, have been used to better electrically isolate interconnects and reduce line-to-line capacitance for 90 nm and below processes, thereby concomitantly reducing resistive capacitance delay (RC delay) which hinders processor speeds. Further reduction of RC delay has been attempted by the introduction of porous ultra low-k dielectric materials (k generally equal to or less than about 2.5) such as Black Diamond II® which is targeted for the newer 45 nm process. Although the porosity introduced into this dielectric further improves interconnect isolation by lowering the dielectric constant k, it also decreases the mechanical modulus making the material more brittle that prior low-k materials and susceptible to damage.
The use of air gaps in semiconductor device packages and structures to enhance interconnect isolation is known. Since air has the lowest k of any material (k=1), a growing trend has been to incorporate air gaps into multi-layered semiconductor structures to isolate interconnects and reduce line-to-line capacitance and RC delay. U.S. Patent Application Publication Nos. 2005/0074960 and 2005/0074961, each incorporated herein by reference in their entireties, describe integration of interconnect isolation air gaps into a semiconductor structure. However, these prior methods are less to ideal. Referring to FIG. 1 showing a prior art design excerpted from Publication No. 2005/0074961, a semiconductor with interconnect air gaps consists of a copper conductor and metal barrier layer (intended to isolate the copper conductor to prevent copper migration into the dielectric material) that lies adjacent to the open space created by the air gap. This arrangement creates EM (electromigration) reliability concerns because the metal conductors lack lateral support and may become easily extruded or deformed into the adjacent open air space in higher current flux situations when the semiconductor device is in use.
An improved multi-layered semiconductor structure with interconnect air gaps and method for fabricating the same is desired.